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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4511 BCD to 7-segment latch/decoder/driver
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
FEATURES * Latch storage of BCD inputs * Blanking input * Lamp test input * Driving common cathode LED displays * Guaranteed 10 mA drive capability per output * Output capability: non-standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with "4511" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4511 are BCD to 7-segment latch/decoder/drivers with four address inputs (D1 to D4), an active LOW latch enable input (LE), an active LOW QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns APPLICATIONS * Driving LED displays
74HC/HCT4511
ripple blanking input (BI), an active LOW lamp test input (LT), and seven active HIGH segment outputs (Qa to Qg). When LE is LOW, the state of the segment outputs (Qa to Qg) is determined by the data on D1 to D4. When LE goes HIGH, the last data present on D1 to D4 are stored in the latches and the segment outputs remain stable. When LT is LOW, all the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BI forces all segment outputs LOW. The inputs LT and BI do not affect the latch circuit.
* Driving incandescent displays * Driving fluorescent displays * Driving LCD displays * Driving gas discharge displays
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Dn to Qn LE to Qn BI to Qn LT to Qn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 24 23 19 12 3.5 64 24 24 20 13 3.5 64 ns ns ns ns pF pF HCT UNIT
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. 3 4 5 7, 1, 2, 6 8 13, 12, 11, 10, 9, 15, 14 16 SYMBOL LT BI LE D1 to D4 GND Qa to Qg VCC NAME AND FUNCTION lamp test input (active LOW) ripple blanking input (active LOW) latch enable input (active LOW) BCD address inputs ground (0 V) segments outputs positive supply voltage
74HC/HCT4511
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
74HC/HCT4511
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS LE X X L L L L L L L L L L L L L L L L H Note 1. Depends upon the BCD-code applied during the LOW-to-HIGH transition of LE. H = HIGH voltage level L = LOW voltage level X = don't care BI X L H H H H H H H H H H H H H H H H H LT L H H H H H H H H H H H H H H H H H H D4 X X L L L L L L L L H H H H H H H H X D3 X X L L L L H H H H L L L L H H H H X D2 X X L L H H L L H H L L H H L L H H X D1 X X L H L H L H L H L H L H L H L H X Qa H L H L H H L H L H H H L L L L L L Qb H L H H H H H L L H H H L L L L L L Qc H L H H L H H H H H H H L L L L L L OUTPUTS DISPLAY Qd H L H L H H L H H L H L L L L L L L
(1)
Qe H L H L H L L L H L H L L L L L L L
Qf H L H L L L H H H L H H L L L L L L
Qg H L L L H H H H H L H H L L L L L L 8 blank 0 1 2 3 4 5 6 7 8 9 blank blank blank blank blank blank
(1)
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
74HC/HCT4511
Fig.5 Logic diagram.
Fig.6 Segment designation.
Fig.7 Display.
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard, excepting VOH which is given below ICC category: MSI Non-standard DC characteristics for 74HC Voltages are referenced to GND (ground = 0 V) Tamb (C) SYMBOL PARAMETER +25 min. VOH VOH HIGH level output voltage HIGH level output voltage 3.98 3.60 5.60 5.48 4.80 typ. 74HC -40 to +85 -40 to +125
74HC/HCT4511
TEST CONDITIONS UNIT VCC (V) V V 4.5 6.0 VI -IO (mA)
max. min. max. min. max. 3.84 3.35 5.45 5.34 4.50 3.70 3.10 5.35 5.20 4.20 VIH or 7.5 VIL 10.0 VIH or 7.5 VIL 10.0 15.0
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay Dn to Qn propagation delay LE to Qn propagation delay BI to Qn propagation delay LT to Qn output transition time 77 28 22 74 27 22 61 22 18 41 15 12 19 7 6 11 4 3 14 5 4 -11 -4 -3 max. 300 60 51 270 54 46 220 44 37 150 30 26 75 15 13 100 20 17 75 15 13 0 0 0 -40 to +85 min. max. 375 75 64 330 68 58 275 55 47 190 38 33 95 19 16 120 24 20 90 18 15 0 0 0 -40 to +125 min. max. 450 90 77 405 81 69 330 66 56 225 45 38 110 22 19 ns
74HC/HCT4511
TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8
tPHL/ tPLH
ns
Fig.9
tPHL/ tPLH
ns
Fig.10
tPHL/ tPLH
ns
Fig.8
tTHL/ tTLH
ns
Figs 8, 9 and 10 Fig.9
tW
latch enable pulse width 80 LOW 16 14 set-up time Dn to LE hold time Dn to LE 60 12 10 0 0 0
ns
tsu
ns
Fig.11
th
ns
Fig.11
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard, excepting VOH which is given below ICC category: MSI Non-standard DC characteristics for 74HCT Voltages are referenced to GND (ground = 0 V) Tamb (C) SYMBOL PARAMETER +25 min. VOH HIGH level output voltage 3.98 3.60 typ. 74HCT -40 to +85 -40 to +125
74HC/HCT4511
TEST CONDITIONS UNIT VCC (V) V 4.5 VI -IO (mA)
max. min. max. min. max. 3.84 3.35 3.70 3.10 VIH or 7.5 VIL 10.0
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT LT, LE BI, Dn UNIT LOAD COEFFICIENT 1.50 0.30
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW propagation delay Dn to Qn propagation delay LE to Qn propagation delay BI to Qn propagation delay LT to Qn output transition time latch enable pulse width LOW set-up time Dn to LE hold time Dn to LE 16 +25 typ. 28 27 23 16 7 5 -40 to +85 max. min. 60 54 44 30 15 20 max. 75 68 55 38 19 24 -40 to +125 min. max. 90 81 66 45 22 ns ns ns ns ns ns
74HC/HCT4511
TEST CONDITIONS UNIT VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS
Fig.8 Fig.9 Fig.10 Fig.8 Figs 8, 9 and 10 Fig.9
tsu th
12 0
5 -4
15 0
18 0
ns ns
4.5 4.5
Fig.11 Fig.11
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
AC WAVEFORMS
74HC/HCT4511
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the input (Dn, LT) to output (Qn) propagation delays and the output transition times.
Fig.9
Waveforms showing the input (LE) to output (Qn) propagation delays and the latch enable pulse width.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the input (BI) to output (Qn) propagation delays.
Fig.11 Waveforms showing the data set-up and hold times for Dn input to LE input.
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
APPLICATION DIAGRAMS
74HC/HCT4511
Fig.12 Connection to common cathode LED display readout.
Fig.13 Connection to common anode LED display readout.
(1) A filament pre-warm resistor to reduce thermal shock and to increase effective cold resistance of the filament is recommended.
Fig.14 Connection to incandescent display readout.
Fig.15 Connection to fluorescent display readout.
Fig.16 Connection to gas discharge display readout.
Fig.17 Connection to LCD display readout. (Direct DC drive is not recommended as it can shorten the life of LCD displays).
December 1990
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Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
74HC/HCT4511
December 1990
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